SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 1 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 20 v (d-s) mosfet marking code : 8410 ordering information : ? SI8410DB-t2-e1 (lead (pb)-free and halogen-free) features ? trenchfet ? power mosfet ? ultra small 1 mm x 1 mm maximum outline ? ultra-thin 0.54 mm maximum height ? material categorization: ? for definitions of compliance please see www.vishay.com/doc?99912 applications ?load switch ? power management ? high speed switching notes a. surface mounted on 1" x 1" fr4 bo ard with full copper, t = 10 s, t a = 25 c. b. maximum under steady state conditions is 100 c/w. c. surface mounted on 1" x 1" fr4 bo ard with minimum copper, t = 10 s. d. maximum under steady state conditions is 190 c/w. e. refer to ipc/jedec ? (j-std-020), no manua l or hand soldering. f. in this document, any reference to case represents th e body of the micro foot de vice and foot is the bump. product summary v ds (v) r ds(on) ( ? ) max. i d (a) a q g (typ.) 20 0.037 at v gs = 4.5 v 5.7 5.9 nc 0.041 at v gs = 2.5 v 5.4 0.047 at v gs = 1.8 v 5.0 0.068 at v gs = 1.5 v 4.2 micro foot ? 1 x 1 bump s ide view 1 g 4 s d 3 d 2 back s ide view 1 1 mm 1 mm 8410 xxx n-channel mosfet s d g absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 20 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t a = 25 c i d 5.7 a a t a = 70 c 4.5 a t a = 25 c 3.8 c t a = 70 c 3.0 c pulsed drain current (t = 100 s) i dm 20 continuous source-drain diode current t c = 25 c i s 1.5 a t a = 25 c 0.65 c maximum power dissipation t a = 25 c p d 1.8 a w t a = 70 c 1.1 a t a = 25 c 0.78 c t a = 70 c 0.5 c operating junction and storage temperature range t j , t stg -55 to 150 c package reflow conditions e vpr 260 ir/convection 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, b t = 10 s r thja 55 70 c/w maximum junction-to-ambient c, d t = 10 s 125 160
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 2 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not su bject to production testing. ? ? ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 20 - - v v ds temperature coefficient ? v ds /t j i d = 250 a -17- mv/c v gs(th) temperature coefficient ? v gs(th) /t j --2.6- gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.4 - 0.85 v gate-source leakage i gss v ds = 0 v, v gs = 8 v - - 100 na zero gate voltage drain current i dss v ds = 20 v, v gs = 0 v --1 a v ds = 20 v, v gs = 0 v, t j = 70 c --10 on-state drain current a i d(on) v ds ? -5 v, v gs = 4.5 v 10 - - a drain-source on-s tate resistance a r ds(on) v gs = 4.5 v, i d = 1.5 a - 0.030 0.037 ? v gs = 2.5 v, i d = 1 a - 0.033 0.041 v gs = 1.8 v, i d = 1 a - 0.038 0.047 v gs = 1.5 v, i d = 0.5 a - 0.044 0.068 forward transconductance a g fs v ds = 10 v, i d = 1.5 a -17- s dynamic b input capacitance c iss v ds = 10 v, v gs = 0 v, f = 1 mhz - 620 - pf output capacitance c oss - 110 - reverse transfer capacitance c rss -40- total gate charge q g v ds = 10 v, v gs = 8 v, i d = 1.5 a - 10.4 16 nc v ds = 10 v, v gs = 4.5 v, i d = 1.5 a -5.99 gate-source charge q gs -0.7- gate-drain charge q gd -0.66- gate resistance r g v gs = 0.1 v, f = 1 mhz -5.3- ? turn-on delay time t d(on) v dd = -10 v, r l = 6.7 ? i d ? 1.5 a, v gen = -4.5 v, r g = 1 ? -510 ns rise time t r -2550 turn-off delay time t d(off) -2650 fall time t f -1020 turn-on delay time t d(on) v dd = -10 v, r l = 6.7 ? i d ? -1.5 a, v gen = -8 v, r g = 1 ? -510 rise time t r -2245 turn-off delay time t d(off) -2345 fall time t f -1020 drain-source body diode characteristics continuous source-drain diode current i s t a = 25 c --1.5 a pulse diode forward current i sm --20 body diode voltage v sd i s = 1.5 a, v gs = 0 -0.71.2v body diode reverse recovery time t rr i f = 1.5 a, di/dt = 100 a/s, t j = 25 c -1530ns body diode reverse recovery charge q rr -615nc reverse recovery fall time t a -8.5- ns reverse recovery rise time t b -6.5-
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 3 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge transfer characteristics capacitance on-resistance vs. junction temperature 0 4 8 12 16 20 0.0 0.5 1.0 1.5 2.0 i d - drain current (a) v d s -drain-to- s ource voltage (v) v gs = 1 v v gs = 5 v thru 2 v v gs = 1.5 v 0.02 0.04 0.06 0.08 0.10 0 4 8 12 16 20 r d s (on) -on-re s i s tance () i d - drain current (a) v gs = 1.8 v v gs = 1.5 v v gs = 4.5 v v gs = 2.5 v 0 2 4 6 8 024681012 v gs - g ate-to- s ource voltage (v) q g -total g ate charge (nc) v d s = 16 v v d s = 5 v v d s = 10 v i d = 1.5 a 0 2 4 6 8 10 0.0 0.3 0.6 0.9 1.2 1.5 i d - drain current (a) v gs - g ate-to- s ource voltage (v) t c = 25 c t c = 125 c t c = -55 c 0 200 400 600 800 048121620 c - capacitance (pf) v d s -drain-to- s ource voltage (v) c i ss c o ss c r ss 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 -50-25 0 255075100125150 r d s (on) -on-re s i s tance (normalized) t j - junction temperature ( c) v gs = 1.8 v, 1.5 v v gs = 4.5 v i d = 1.5 a v gs = 2.5 v
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 4 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient safe operating area, junction-to-ambient 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - s ource current (a) v s d - s ource-to-drain voltage (v) t j = 150 c t j = 25 c 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 150 v gs (th) (v) t j - temperature ( c) i d = 250 a 0 0.02 0.04 0.06 0.08 0.10 012345 r d s (on) -on-re s i s tance () v gs - g ate-to- s ource voltage (v) t j = 125 c t j = 25 c i d = 1.5 a 0 5 10 15 20 25 power (w) time (s) 10 1000 0.1 0.01 0.001 100 1 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v d s -drain-to- s ource voltage (v) * v gs > minimum v gs at which r d s (on) i s s pecified 100 s limited by i dm limited by i d(cont) limited by r d s (on) * 1 m s t a = 25 c bvd ss limited 10 m s 100 m s 10 s , 1 s dc
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 5 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) current derating* power derating note ? when mounted on 1" x 1" fr4 with full copper. * the power dissipation p d is based on t j (max.) = 150 c, using junction-to-case thermal resistance, and is more useful in se ttling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. 0 1 2 3 4 5 6 0 25 50 75 100 125 150 i d - drain current (a) t a -ca s e temperature ( c) 0.0 0.3 0.6 0.9 1.2 1.5 25 50 75 100 125 150 t a - ambient temperature (c) power dissipation (w)
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 6 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient (1" x 1" fr4 board with full copper) normalized thermal transient impedance, junction-to-ambient (1" x 1" fr4 board with minimum copper) 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 100 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 190 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05
SI8410DB www.vishay.com vishay siliconix s14-1067-rev. a, 19-may-14 7 document number: 62961 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline micro foot 1 mm x 1 mm: 4-bump (0.5 mm pitch) notes (1) laser mark on the backside surface of die. (2) bumps are 95.5 % sn, 3.8 % ag, 0.7 % cu. (3) ? is location of pin 1. (4) b1 is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. (5) non-solder mask defi ned copper landing pad. note a. use millimeters as the primary measurement. ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62961 . dimension millimeters a inches minimum nominal maximum minimum nominal maximum a 0.460 0.500 0.540 0.0181 0.0196 0.0212 a1 0.214 0.250 0.286 0.0084 0.0098 0.0112 a2 0.244 0.254 0.264 0.0096 0.0100 0.0104 b 0.297 0.330 0.363 0.0116 0.0129 0.0142 b1 0.250 0.0098 e 0.500 0.0197 s 0.210 0.230 0.250 0.0008 0.0090 0.0098 d 0.920 0.960 1.000 0.0362 0.0377 0.0393 k 0.028 0.065 0.101 0.0011 0.0025 0.0039 d e s a a1 a2 s d e 8410 xxx mark on back s ide of die s g d s note 4 b k 4 x ?b1 b1
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